1. Field of the Invention
Embodiments of the present invention relate generally to the field of communications. More particularly, embodiments of the present invention relate to the field of demodulating differentially encoded phase shift keyed signals.
2. Background of the Invention
Modern communication systems generally require that data be transmitted over distances from a transmitter to a receiver. To conduct communications over such distances, which can be substantial, the data must be modulated on to a carrier frequency in a transmitter, sent to a receiver and then demodulated by the receiver. Numerous modulation techniques are known for carrying out communications over such distances.
Where the data is digital, the information content is carried in binary digits called bits. The bits are combined to form words, which are combined in various ways to carry the desired information. In modern communication systems, symbols representative of one or more bits are sent from the transmitter to the receiver. Communication efficiencies, including bandwidth, power and channel frequency conservation can be gained by choosing symbols that represent a plurality of bits of information.
A variety of modulation techniques exist whereby a symbol can carry information corresponding to one or more bits of information. Such modulation techniques are generally referred to as M-ary modulation, where the M indicates the number of valid symbols in the modulation scheme. For example, in 8-ary modulation, there are 8 valid symbols, each symbol corresponding to 3 bits of information. The symbols are states that can be represented in various forms. For example, the symbols can be represented by phase offsets, frequency offsets, amplitudes or any other quantifiable measure.
One such M-ary technique is M-ary differential phase shift keying (DPSK). M-ary differential phase shift keying is a well known modulation technique that can be used in numerous communication applications. In DPSK systems, symbols are represented by relative phase shifts in the signal from one symbol to the next symbol. Where M is 8 for example, there are 8 valid symbols, each of which corresponds to 3 bits of information. This form of M-ary differential phase shift keying is known as D8PSK. An exemplary bit assignment to 8 valid symbols for a typical D8PSK implementation is illustrated in FIG. 1.
Typically, demodulation of a DPSK signal requires comparing a sample of the signal in a current symbol interval to a sample of the signal that occurred in the previous symbol interval. The comparison provides an estimate of the relative difference from one symbol to the next. The relative phase difference can be mapped to an absolute phase, which then can be mapped to symbols and corresponding bits.
An exemplary conventional DPSK demodulator is illustrated schematically in FIG. 2. A sampled input signal is delayed in delay 203 and conjugated in conjugator 204. The delayed input signal is compared to a current version of the signal in phase comparator 206. The delay is typically one symbol interval in time. In this manner, the current symbol is compared to the prior symbol to determine relative phase difference between the current and previous symbol.
Conventional DPSK demodulators can also include a best sample selection circuit. In a practical DPSK demodulator, a plurality of samples are taken during the time interval of one symbol. This process is generally known as oversampling. The best sample selection circuit determines which sample of the plurality of samples taken per symbol is the best sample to use for further processing. A header consisting of a known sequence of symbols is sent by the transmitter so that the receiver can be synchronized to the transmitted signal. Best sample selector 210 determines the best sample to use based on a correlation of the input signal with this known header that is performed in a correlator 212. If the correlation is above a certain threshold, for example, 80% as determined by a threshold detector 214, the best sample is determined to be that sample which results in the correlation being above the threshold.
Once determined, the particular signal sample to use for further processing is selected using an input gate 208. Input gate 208 is controlled using a gate control signal output from a best sample selector 210. At this point, the threshold circuit turns off the best sample determination process by throwing a switch 216 as the best sample is now known.
In the circuit shown in FIG. 2, correlation is performed on each sample. The correlation and best sample selection processes are very expensive computationally because all computations must be completed with one sample interval. For example, if the header is 80 symbols in length, and the sampling rate is 10 times per symbol, then 800 correlations must be performed every sample interval to determine the best sample. Although processing of the signal subsequent to best sample selection may require significantly fewer calculations per symbol, the correlation and best sample selection processes require a very high minimum processor speed that can be employed to demodulate the signal. This high degree of computation in a short period consumes significant battery power and continues to consume battery power at a high rate even after the correlation and best sample selection processes are completed.
Correlator 212 also provides input to a frequency offset estimator 218. Frequency offset estimator 218 determines whether there is any frequency offset between a local oscillator and the received carrier frequency. Such a frequency offset manifests itself as a progressive phase shift across the samples corresponding to a particular symbol. The progressive phase shift looks like a slope or tilt when plotted versus time across the phase estimates of a symbol. Frequency offset estimator 218 determines the amount of progressive phase shift across the samples of the symbol. Using the progressive phase shift information determined by frequency estimator 218, a frequency correction is calculated in a phase adjuster 220 for each sample of the symbol. The quantities Zq(t) and Zi(t) shown in phase adjuster 220 of FIG. 2 refer to the quadrature and in-phase components of each sample of the symbol.
A circuit 222 determines in which quadrant the phase estimate of the current symbol lies. This is necessary to correct for limitations in typical mathematical functions libraries when used in signal processing applications. The demodulated phase is corrected for frequency offset in phase adder 223. A phase offset correction circuit 224 takes the raw phase data and determines the initial phase. A symbol mapping circuit 226 maps the absolute phase to the appropriate demodulated symbol, which is representative of one or more data bits.
Conventional DPSK demodulators, such as DPSK demodulator 202 illustrated in FIG. 2, use complex mathematics in the correlation of the samples in the message header to determine frequency offset and to demodulate phase angles. Such complex mathematics is computationally expensive, and as a result consume significant amounts of power.
Moreover, once the correlation of the header samples is performed to determine frequency offset, conventional DPSK demodulators no longer check for frequency offset. Rather, they only perform message demodulation under the assumption that the frequency offset will not vary significantly over the duration of the message. Often, this assumption is not valid, and communication quality degrades significantly. Consequently, the ability to track phase and frequency offset errors, which are calculated only from the header correlation, is lost. As a result, additional phase angle and frequency error acquisition and tracking circuitry is often required. Such additional circuitry is also computationally very expensive and consequently, requires a great deal of power.